1. Field of the Invention
This invention relates generally to integrated semiconductor structures including fabrication methods therefor and, more particularly, to integrated NPN semiconductor transistor structures using PN junction substrate isolation and dielectric sidewall isolation including the fabrication methods therefor.
2. Background of the Prior Art
In the past, integrated semiconductor structures were fabricated using PN junction isolation in order to electrically isolate various transistor or other devices (diodes, resistors, etc.) from each other. The PN junction isolated devices usually had a substrate of one type conductivity and the device having a collector or other region of opposite type conductivity was located on the substrate and biased with respect to the substrate in a manner to utilize the PN junction between the substrate and the device for electrically isolating the device from the substrate.
Other techniques for isolating devices in an integrated semiconductor substrate were developed including the concept of dielectric isolation. In this technique of isolation, the various semiconductor devices were formed in monocrystalline pockets of semiconductor material which were isolated from a substrate by means of a dielectric material, usually silicon dioxide. The dielectric isolated devices have an advantage over junction isolated devices in the elimination of the bias needed to set up the PN junction isolation and also in the avoidance of the possible breakdown of the PN junction.
Combinations of PN junction isolated structures and dielectric isolated regions were utilized to provide integrated semiconductor structures using the benefits of both isolation techniques. The advantage of the PN junction isolated structure is that it can be generally made more planar and with less fabrication steps than the more complex dielectric substrate isolated devices.
One recently developed technique used in the combination of PN junction and dielectric isolated structures produced the "VIP" semiconductor structure wherein a V-shaped moat which was formed around the individual transistor devices was subsequently filled by means of a V-shaped silicon dioxide Isolation layer followed by a filled-in Polycrystalline silicon semiconductor material which thereby formed the "VIP" isolation channel.
However, in designing and utilizing the "VIP" integrated semiconductor structures, it was discovered that leakage paths developed between supposedly electrically isolated semiconductor devices thereby destroying their electrical isolation and resulted in the breakdown of the usefulness of the integrated circuit. Accordingly, a need existed to develop a new type of "VIP" semiconductor structure which would have higher reliability and avoid the problems of leakage and the resultant breakdown of the electrical isolation features of the integrated semiconductor structure.